Featured in this episode of Tech News of the Week
Chip designers Ventana have published a spec for their next generation of RISC-V datacenter chips called the Veyron V2. These chips use the new Universal Chiplet Interconnect Express standard instead of the Bunch of Wires standard (yes, that is a real thing) used by the V1 version of the chip.
UCI-Express was created by Intel and has the industry backing of AMD, Arm, and Google to list a few. Also included in the chip design is a new and improved 512-bit vector extension, which allows the chip to run some AI calculations locally instead of farming it out to an accelerator card, aka a bunch of expensive Nvidia GPUs.
The cores of the V2 are more efficient that the previous design, offering a 20% improvement in instructions per clock cycle. And speaking of cores, the Veyron V2 will have up to 192 cores packages in 6 32-core chiplets.
The target for these chip designs is hyperscalers, who are looking to implement ever greater control over their hardware stack and lower costs paid to other vendors like Intel or ARM. The designs will be production ready sometime in Q3 of 2024, at which time the hyperscalers can begin to fab custom chips based on the design.
Seems like this RISC-V thing is quickly becoming a reality. Now you’ll pardon me as I take a (V)ictory lap.